Experimental Platform for the Study of the Effect of PRNGs on Random Time-Interleaved ADC Systems
DOI:
https://doi.org/10.37537/rev.elektron.10.1.226.2026Keywords:
FPGA, PRNG, TIME-INTERLEAVING, TIME-INTERLEAVED ADC, ADCAbstract
This work describes the design and implementation of an experimental test bench aimed at analyzing the effect that the randomness of channel selection sequences exerts on the Spurious-Free Dynamic Range (SFDR) in time-interleaved sampling architectures.
The system is composed of control logic implemented in a DE0-Nano FPGA, together with a PC interface that allows sending to the board pseudo-random sequences generated by the user and controlling the number of acquired samples. In addition, the structure necessary to store the samples in the SDRAM memory integrated in the DE0-Nano and to perform part of the data processing is developed in VHDL. Altogether, this test bench constitutes an efficient platform for the evaluation of the SFDR.
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Data Availability Statement
The data that support the findings of this study are available from the corresponding author upon reasonable request.
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Copyright (c) 2026 Ezequiel Dario Rodriguez, Matias Medina, Lucas Andres Rabioglio, Celeste Cebedio, Luciana De Micco
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