FPGA Algorithm Implementation for Parasitic Analysis
DOI:
https://doi.org/10.37537/rev.elektron.6.1.149.2022Keywords:
Parasitic Analysis, Image Processing, HLS, FPGAAbstract
An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm using high-level synthesis. The results demonstrate the feasibility of the implementation, with an 87% accuracy operating at a rate of up to 65 frames per second and an occupation of LUTs less than 45%, considering two commercial kits (PYNQ-Z1 and ULTRA96V2).Downloads
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