Daisy Chain Topology on FPGA for naval modernization: implementation and extension with ARP

Authors

  • Emiliano Sebastián Gallo Universidad Tecnológica Nacional F.R.B.B.
  • Ricardo Luis Cayssials Universidad Tecnológica Nacional F.R.B.B.
  • Christian Luis Galasso Universidad Tecnológica Nacional F.R.B.B. Universidad de la Defensa Nacional – FADARA – ESOA Servicio de Análisis Operativos, Armas y Guerra Electrónica de la Armada
  • Alan Emir Arias Universidad Tecnológica Nacional F.R.B.B.

DOI:

https://doi.org/10.37537/rev.elektron.9.2.220.2025

Keywords:

Daisy Chain, digital design, FPGA, modernization, VHDL

Abstract

Operational consoles, human-machine interfaces implemented in Surface Units of the Naval Fleet Command, facilitate the visualization of critical data and system management through operator command input. However, their operability and upgrade potential are restricted by dependence on proprietary hardware. This report describes a component of a broader project whose purpose is to replace the "Optronic Sensor Control Console" (CCSO) with a commercial computer (PC). This modernization seeks to adapt the system to new operational demands, enable the incorporation of new functionalities, and eliminate dependence on proprietary components. This article specifically addresses the operational logic of a Daisy Chain topology, used as an interconnection strategy between devices. Its concept, digital implementation in VHDL, and validation through a SystemVerilog testbench are presented, highlighting its role in the proposed architecture.

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Author Biography

  • Emiliano Sebastián Gallo, Universidad Tecnológica Nacional F.R.B.B.
    Ingeniero electronico, docente e investigador.

References

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​ C. Galasso y G. Friedrich, “FPGA del Kit al prototipo,” en Congreso Argentino de Sistemas Embebidos (CASE), Argentina, 2013, p. 50.

​ E. Gallo, R. Cayssials, C. Galasso, y A. Arias, “Implementación de Daisy Chain en VHDL,” en Congreso Argentino de Sistemas Embebidos (CASE), Argentina, 2025, pp. 23–26.

​ Analog Devices, “Daisy Chain.” [Online]. Available: https://www.analog.com/en/resources/glossary/daisy_chain.html

​ E. Gallo, R. Cayssials, C. Galasso, y A. Arias, “Lógica de funcionamiento Daisy Chain,” en Congreso Virtual de Microcontroladores y sus Aplicaciones, Argentina, 2025, aceptado para publicación.

​ C. Galasso, A. Laiuppa, J. Ermantraut, S. Leoni, D. Martinez, y M. Paz, “Aplicación práctica de co-diseño de HW y SW para la apertura de un sistema de tiempo real,” en 53° JAIIO – SAIC, Simposio Argentino de Ingeniería en Computación, Argentina, 2024, pp. 67–80.

​ Texas Instruments, "BQ79616-Q1 Daisy Chain Communications," Application Report SLVAEP4, 2019. [Online]. Available: https://www.ti.com/lit/an/slvaep4/slvaep4.pdf

​ M. M. Mano y M. D. Ciletti, “Digital Design with an Introduction to the Verilog HDL, VHDL, and SystemVerilog,” 6th ed., Pearson, 2017.

Ansys, “What is Hardware-in-the-Loop Testing?” [Online]. Available: https://www.ansys.com/simulation-topics/what-is-hardware-in-the-loop-testing

​ Xilinx Inc. “XC6SLX45T-2FGG484I – Spartan-6 FPGA Family,” Product Specification DS160, 2011. [Online]. Available: https://docs.amd.com/v/u/en-US/ds160

​STMicroelectronics, "STM32F429ZI High-performance STM32F4 MCU with DSP and FPU," Datasheet DS8626, Rev 9, 2024.

Published

2025-12-15

Issue

Section

Optoelectronics and Microelectronics

How to Cite

[1]
E. S. Gallo, R. L. Cayssials, C. L. Galasso, and A. E. Arias, “Daisy Chain Topology on FPGA for naval modernization: implementation and extension with ARP”, Elektron, vol. 9, no. 2, pp. 56–67, Dec. 2025, doi: 10.37537/rev.elektron.9.2.220.2025.