Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
DOI:
https://doi.org/10.37537/rev.elektron.8.2.201.2024Keywords:
advanced encryption standard (AES), counter mode (CTR), field programable gate array (FPGA), System on Chip (SoC), Zynq7000, XilinxAbstract
Cryptography plays a crucial role in protecting information on public networks. The implementation of AES with CTR on Xilinx SoC-FPGA devices, such as Zynq 7000 and Kintex 7, aims to enhance security in IoT devices and embedded systems. The goal is to ensure data confidentiality and availability in connected environments, prioritizing low area usage, low power consumption, and high performance. Implementation was made using a Very High-Speed Integrated Circuit Hardware Description Language (VHDL) on Vivado 2019-2. The results show its area utilization for AES and AES-CTR implementations, with a throughput of 1.8 and 7.67 Gbps for Zynq 7000 and, 2.72 and 11.11 Gbps for Kintex 7; they are also presented for a 128-bits key size and four CTR blocks. VHDL generics can be configured to be 192-bit and 256-bit lengths with different block sizes. Implemented AES-CTR IP showed correct behavior for 128, 192, and 256 key sizes with four CTR blocks. A cipher process with sizes 192 and 256 requires additional cycles that affect the timing performance and hardware utilization.Downloads
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