A Comparative Study between HLS and HDL on
SoC for Image Processing Applications
Un Estudio Comparativo entre HLS y HDL en SoC para Aplicaciones de Procesamiento de Imágenes
Roberto Millón
, Emmanuel Frati
and Enzo Rucci
Departamento de Ciencias Básicas y Tecnológicas, UNdeC
Chilecito (5360), La Rioja, Argentina
III-LIDI, Facultad de Informática, UNLP - CIC.
50 y 120 s/n, La Plata (1900), Argentina
Abstract—The increasing complexity in today’s systems
and the limited market times demand new development tools
for FPGA. Currently, in addition to traditional hardware
description languages (HDLs), there are high-level synthesis
(HLS) tools that increase the abstraction level in system
development. Despite the greater simplicity of design and
testing, HLS has some drawbacks in describing hardware.
This paper presents a comparative study between HLS
and HDL for FPGA, using a Sobel filter as a case study
in the image processing field. The results show that the
HDL implementation is slightly better than the HLS version
considering resource usage and response time. However,
the programming effort required in the HDL solution is
significantly larger than in the HLS counterpart.
Keywords: FPGA; SoC; Sobel; HDL; HLS.
Resumen— La creciente complejidad de los sistemas
actuales y los tiempos limitados del mercado exigen nuevas
herramientas de desarrollo para las FPGAs. Hoy en día,
además de los tradicionales lenguajes de descripción de
hardware (HDL), existen herramientas de síntesis de alto nivel
(HLS) que aumentan el nivel de abstracción en el desarrollo
de sistemas. A pesar de la mayor simplicidad de diseño y
pruebas, HLS tiene algunos inconvenientes para describir
hardware. Este documento presenta un estudio comparativo
entre HLS y HDL para FPGA, utilizando un filtro Sobel
como caso de estudio en el ámbito del procesamiento de
imágenes. Los resultados muestran que la implementación
HDL es levemente mejor que la versión HLS considerando
uso de recursos y tiempo de respuesta. Sin embargo, el
esfuerzo de programación en la implementación de HDL es
significativamente mayor.
Palabras clave: FPGA; SoC; Sobel; HDL; HLS.
FPGAs are in an intermediate position between ASICs
and CPUs, given their ability to reconfigure their archi-
tecture according to the application and their good energy
efficiency [1]. In the last decade, multiple efforts have
been made to reduce the energy consumption of large
computing systems [2] and FPGAs are consolidating as a
viable alternative to achieve this goal. That is why several
companies and organizations have incorporated this kind
of hardware devices to their systems, like Microsoft [3],
Baidu [4], CERN [5] or Amazon [6].
However, FPGAs have not been massively adopted as it
was originally expected by their vendors [7]. At the begin-
ning and for more than one decade, FPGA applications were
exclusively developed using hardware description languages
(HDLs). Unfortunately, HDLs have many drawbacks: they
are verbose and error-prone, require in-depth knowledge of
digital electronics, and demand long development times [8].
As a result, the FPGA community explored alternative
tools to increase the abstraction level as a way to reduce
programming costs and accelerate time to market [9].
Since the early 2000s, several FPGA vendors started to
offer high-level synthesis (HLS) tools for systems devel-
opment. In the HLS approach, programmers code FPGA
applications using high-level languages (HLLs), like C, C++,
or SystemC. Then, the tool is responsible for generating the
corresponding HDL code [10]. Thus, engineers work at a
higher abstraction level and produce reusable hardware de-
signs without requiring hardware expertise. This alternative
approach allowed the industry to shorten time to market
since productivity gets increased while development cost
gets reduced [11].
Even though HLS tools present several advantages to
develop hardware descriptions, they also have a weak spot.
As HLLs were designed for software applications, they
present some shortcomings when describing hardware that
can negatively impact the resources usage and response time
of the final hardware designs [12].
In this context, it is important to know the advantages and
disadvantages of different languages and approaches to syn-
thesize optimal hardware descriptions. This paper presents
a comparative study between two Sobel filter solutions for a
System-on-Chip (SoC) platform using both HDL and HLS
approaches. Overall, the main contributions of the paper are
the following:
The creation of a public git repository containing opti-
mized SoC solutions of Sobel filter for edge detection
using both HDL and HLS approaches
. As Sobel is
a convolutional operator, these implementations can
be easily adapted to perform other image processing
Revista elektron, Vol. 4, No. 2, pp. 100-106 (2020)
ISSN 2525-0159
Recibido: 23/10/20; Aceptado: 27/11/20
Creative Commons License - Attribution-NonCommercial-
NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
Original Article
A thorough comparison between both solutions in
terms of resource usage, execution time, and program-
ming effort. In this way, we can identify the strengths
and weaknesses of each programming approach in the
image processing field.
The rest of the paper is organized as follows. Section II
presents the background and the state of the art of this work.
The optimized implementations are described in Section III.
In Section IV, experimental results are analyzed and finally,
in Section V, conclusions and some ideas for future research
are summarized.
A. FPGA Programming Languages
Verilog and VHDL are the two leading HDLs to describe,
simulate, and synthesize hardware systems. Both were devel-
oped in the 80’s and have been updated several times since
then [13]. Using HDL to describe hardware requires digital
design expertise, which limits the use of FPGA to hardware
engineers. The results are low-level, complex designs, and
slow development and debugging processes.
The HDL drawbacks lead to the development of new tools
to describe hardware in the early 2000s, such as Vivado HLS
(Xilinx), Catapult C (Mentor Graphics), and Intel OpenCL
SDK (Intel). These HLL-based tools raise the abstraction
level and increase FPGA opportunities to engineers that
specialize in embedded software programming [14].
Unfortunately, C-based languages have some shortcom-
ings when describing hardware. First, either the designer or
the HLS tool must specify the concurrency model because
of HLLs lack a definition of hardware timing. Second,
HLLs lack of the definition of exact bit width for a signal,
since they only provide limited data types such as bool,
int, and/or long. Third, HLLs do not have abstractions of
hardware interfaces and, contrary to the distributed memory
model of FPGAs, they assume a flat memory model that
can be accessed through pointers. Therefore, HLS tools must
provide extensions to the HLL through libraries and directive
sets to overcome those deficiencies. In other cases, HLS
tools impose restrictions on HLLs, such as not supporting
dynamic memory allocations [12].
B. Sobel Filter
The Sobel algorithm is a gradient-based edge detection
method to extract the edges of a grayscale image using
the first derivative. By computing horizontal h and vertical
v direction derivatives of a pixel against the surrounding
pixels, the algorithm segments the image into areas or
objects. This process reduces the amount of data while
preserving the image’s structural properties. The G
derivatives represent the components of the gradient
vector [15], [16], given by Equation 1.
f = ( G
, G
) (1)
The gradient magnitude expresses the rate of change of
intensity in neighboring pixels and defines the edge strength.
A sudden change in contiguous pixels increases the gradient
magnitude resulting in the border of an object, given by
Equation 2:
|∇f| =
+ G
Equation 2 can be approximated as Equation 3. This last
formula delivers a faster computation but still preserving
relative changes in intensity.
|∇f| |G
| + |G
| (3)
Fig. 1 shows the two 3×3 convolution masks (namely, M
and M
) used by the Sobel filter to calculate the components
of the gradient vector.
Fig. 1. Sobel convolution masks
From mathematical point of view, the image must be
multiplicated by the Sobel masks to get the components of
the gradient vector. The image is scanned from left to right
and top to bottom, applying convolution to each individual
pixel using the M
and M
masks [17]. Fig. 2 shows the
convolution process of the Sobel filter.
Fig. 2. Sobel convolution process
C. State of the Art
In the literature, numerous works propose HLS or HDL
solutions to different problems. However, just a few im-
plement the same algorithm with both HLS and HDL de-
scriptions. Some studies conclude that both implementations
have similar performance results with a larger resource con-
sumption on the HLS approach [8], [18]–[22]. Conversely,
other studies observed better performances in one of the
two implementations, either HLS [23]–[27] or HDL [28],
[29]. From the programming effort perspective, comparative
works between HLS and HDL designs for FPGA show
similar trends (except for [30]). In general, HLS descriptions
require less development time due to their higher abstraction
level and the programmer’s familiarity with those languages.
However, there is no single conclusion about performance
and resource usage between the two approaches. In these as-
pects, the results are affected by the problem characteristics,
the tools used, and the design features.
This research presents and compares two optimized Sobel
filter solutions for a SoC platform designed with both HLS
and HDL approaches. Compared to previous works, the
novelty of this study lies in the hardware and software
Revista elektron, Vol. 4, No. 2, pp. 100-106 (2020)
ISSN 2525-0159