Un estudio comparativo entre HLS y HDL en SoC para aplicaciones de procesamiento de imágenes
Resumen
Palabras clave
Referencias
A. Putnam, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. M. Caulfield, A. Smith, J. Thong, P. Y. Xiao, D. Burger, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, and G. P. Gopal, “A reconfigurable fabric for accelerating large-scale datacenter services,” Communications of the ACM, vol. 59, no. 11, pp. 114–122, Oct. 2016. [Online]. Available: http://dl.acm.org/citation.cfm?doid=3013530.2996868
P. Czarnul, J. Proficz, and A. Krzywaniak, “Energy-aware highperformance computing: Survey of state-of-the-art tools, techniques, and environments,” Scientific Programming, vol. 2019, p. 8348791, Apr 2019. [Online]. Available: https://doi.org/10.1155/2019/8348791
P. Hernandez, “Microsoft Uses Intel FPGAs for Smarter Bing Searches,” 2018. [Online]. Available: https://www.eweek.com/cloud/microsoft-uses-intel-fpgas-for-smarter-bing-searches
X. Inc., “Baidu Deploys Xilinx FPGAs in New Public Cloud Acceleration Services.”
L. Barney, “CERN openlab Explores New CPU/FPGA Processing Solutions,” Apr. 2017. [Online]. Available: https://www.hpcwire.com/2017/04/14/xeon-fpga-processor-tested-at-cern/
K. Freund, “Amazon And Xilinx Deliver New FPGA Solutions,” 2017. [Online]. Available: https://bit.ly/3ofmBsI
R. Tessier, K. Pocek, and A. DeHon, “Reconfigurable Computing Architectures,” Proceedings of the IEEE, vol. 103, no. 3, pp. 332–354, Mar. 2015.
M. D. Zwagerman, “High level synthesis, a use case comparison with hardware description language,” mastersthesis, School of Engineering, Grand Valley State University, 2015.
S. Windh, X. Ma, R. J. Halstead, P. Budhkar, Z. Luna, O. Hussaini, and W. A. Najjar, “High-Level Language Tools for Reconfigurable Computing,” Proceedings of the IEEE, vol. 103, no. 3, pp. 390–408, Mar. 2015. [Online]. Available: http://ieeexplore.ieee.org/document/7086410/
G. Martin and G. Smith, “High-level synthesis: Past, present, and future,” IEEE Des. Test, vol. 26, no. 4, pp. 18–25, 2009, conference Name: IEEE Design Test of Computers.
R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y. T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, and K. Bertels, “A survey and evaluation of FPGA high-level synthesis tools,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 10, pp. 1591–1604, 2016.
H. Ren, “A brief introduction on contemporary High-Level Synthesis,” in 2014 IEEE International Conference on IC Design & Technology. Austin, TX, USA: IEEE, May 2014, pp. 1–4. [Online]. Available: http://ieeexplore.ieee.org/document/6838614/
D. Harris and S. Harris, Digital Design and Computer Architecture (Second Edition). Morgan Kaufmann, 2013.
F. A. Escobar, X. Chang, and C. Valderrama, “Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC,” IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 2, pp. 600–612, Feb. 2016. [Online]. Available: http://ieeexplore.ieee.org/document/7051218/
F. M. Vallina, C. Kohn, and P. Joshi, “Zynq all programmable SoC sobel filter implementation using the vivado HLS tool,” 2012. [Online]. Available: https://bit.ly/3h6egD1
Y. Zheng, “The design of sobel edge extraction system on FPGA,” ITM Web Conf., vol. 11, 2017. [Online]. Available: https://doi.org/10.1051/itmconf/20171108001
N. Nausheen, A. Seal, P. Khanna, and S. Halder, “A FPGA based implementation of Sobel edge detection,” Microprocess. Microsyst., vol. 56, p. 84–91, Feb. 2018.
J. Hiraiwa and H. Amano, “An FPGA Implementation of Reconfigurable Real-Time Vision Architecture,” in 2013 27th International Conference on Advanced Information Networking and Applications Workshops, Mar. 2013, pp. 150–155.
K. Hill, S. Craciun, A. George, and H. Lam, “Comparative analysis of opencl vs. hdl with image-processing kernels on stratix-v fpga,” in 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015, pp. 189–193.
G. Wang, H. Lam, A. George, and G. Edwards, “Performance and productivity evaluation of hybrid-threading hls versus hdls,” in 2015 IEEE High Performance Extreme Computing Conference (HPEC), 2015, pp. 1–7.
A. Stanciu and C. Gerigan, “Comparison between implementations efficiency of HLS and HDL using operations over Galois Fields,” in 2017 IEEE 23rd International Symposium for Design
and Technology in Electronic Packaging (SIITME). Constanta, Romania: IEEE, Oct. 2017, pp. 171–174. [Online]. Available: http://ieeexplore.ieee.org/document/8259883/
I. Stamoulias, C. Kachris, and D. Soudris, “Hardware accelerators for financial applications in HDL and High Level Synthesis,” in 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul. 2017, pp. 278–285.
A. Cornu, S. Derrien, and D. Lavenier, “Hls tools for fpga: Faster development with better performance,” in Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg, 2011. [24] J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avižienis, J. Wawrzynek, and K. Asanovic, “Chisel: Constructing hardware in ´ a scala embedded language,” in DAC Design Automation Conference 2012, 2012, pp. 1212–1221.
O. Arcas-Abella, G. Ndu, N. Sonmez, M. Ghasempour, A. Armejach, J. Navaridas, Wei Song, J. Mawer, A. Cristal, and M. Luján, “An empirical evaluation of high-level synthesis languages and tools for database acceleration,” in 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8.
M. Gurel, “A comparative study between rtl and hls for image processing applications with fpgas,” Master’s thesis, UNIVERSITY OF CALIFORNIA, SAN DIEGO, UC San Diego, 2016,
https://escholarship.org/uc/item/9vx1s37b.
M. Pelcat, C. Bourrasset, L. Maggiani, and F. Berry, “Design productivity of a high level synthesis compiler versus HDL,” in 2016 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation (SAMOS). Agios Konstantinos, Samos Island, Greece: IEEE, Jul. 2016, pp. 140–147. [Online]. Available: http://ieeexplore.ieee.org/document/7818341/
M.-A. Tétrault, “Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications,” in 2018 21st IEEE NPSS Real Time Conference. Williamsburg: IEEE, Jun. 2018, p. 3.
G. Akkad, A. Mansour, B. ElHassan, F. L. Roy, and M. Najem, “Fft radix-2 and radix-4 fpga acceleration techniques using hls and hdl for digital communication systems,” in 2018 IEEE International Multidisciplinary Conference on Engineering Technology (IMCET), 2018, pp. 1–5.
D. Aledo, B. Carrion Schafer, and F. Moreno, “VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks,” IEICE Transactions on Information and Systems, vol.
E102.D, no. 3, pp. 512–521, Mar. 2019. [Online]. Available: http://dx.doi.org/10.1587/transinf.2018EDP7142
R. Millon, E. Frati, and E. Rucci, “Implementación de Filtro de Detección de Bordes Sobel en SoC usando Síntesis de Alto Nivel,” in Actas del Congreso Argentino de Sistemas Embebidos (CASE 2020), 2020, pp. 73–75.
A. Nosrat and Y. S. Kavian, “Hardware description of multidirectional fast sobel edge detection processor by VHDL for implementing on FPGA,” International Journal of Computer
Applications, vol. 47, no. 25, pp. 1–7, 2012. [Online]. Available: http://research.ijcaonline.org/volume47/number25/pxc3879872.pdf
R. Mehra and R. Verma, “Area efficient FPGA implementation of sobel edge detector for image processing applications,” International Journal of Computer Applications, vol. 56, no. 16, pp. 7–11, 2012. [Online]. Available: http://research.ijcaonline.org/volume56/number16/pxc3883086.pdf
G. Chaple and R. D. Daruwala, “Design of Sobel operator based image edge detection algorithm on FPGA,” in 2014 International Conference on Communication and Signal Processing. Melmaruvathur, India: IEEE, apr 2014.
K. Bhatt, V. Tarey, and P. Patel, “Analysis of source lines of code(SLOC) metric,” nternational Journal of Emerging Technology and Advanced Engineering, vol. 2, 2012.
DOI: https://doi.org/10.37537/rev.elektron.4.2.117.2020
Enlaces de Referencia
- Por el momento, no existen enlaces de referencia
Copyright (c) 2020 Enzo Rucci
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Revista elektron, ISSN-L 2525-0159
Facultad de Ingeniería. Universidad de Buenos Aires
Paseo Colón 850, 3er piso
C1063ACV - Buenos Aires - Argentina
revista.elektron@fi.uba.ar
+54 (11) 528-50889