
The utilization of hardware resources, such as Slice
Registers, Slice LUTs, and overall slices, was calculated for
the implemented design of AES-CTR across different
devices. The xc7z020clg484-1 device shows a Slice
Register utilization of 1.03%, while xc7k325tffg676-1
reflects a much lower utilization at 0.26%. Similarly, Slice
LUT usage for the devices was 16.49% and 3.68%,
respectively. These figures indicate that the implementation
efficiency varies based on the device.
In terms of utilization and performance of AES
implementations on Xilinx SoC-FPGA and Kintex 7 devices,
Table V compares these results with other works. The two
devices in this study exhibit the lowest GBPS values
compared to those in the literature. There is limited
information available on AES implementations using a non-
pipelined approach for SoC and Kintex devices. However,
this work demonstrates lower resource utilization compared
to pipelined implementations, providing more room for
additional logic integration.
Silitonga et al. [8] This work Sikka et al. [5] This work
zynq7000 zedboard xc7z020clg484-1 xc7k70t-fbg676 xc7k325tffg676-1
Blocks 4 4 1 4
Slice Register 6 1095 (1.03) 449 1076 (0.26)
Slice LUT 46 8772 (16.49) 585 7498 (3.68)
Slices - 2445 (18.38) - 2182 (4.28)
538.38 7.67 38.05 11.11
- 164.9 297.3 238.7
Table I. Comparison AES and AES-CTR
V. CONCLUSION
The integration of SoC devices in IoT networks
improves hardware-software consistency but limits system
space and compatibility with other components. Two
sequential AES implementation strategies were compared:
non-pipelined and pipelined. While pipelined
implementations offer higher throughput, they increase area
utilization, whereas the proposed method significantly
reduces area usage on the Zynq7000 SoC, albeit with
slightly lower throughput. This approach is suitable for
interconnected device communication applications.
Performance can be enhanced by implementing AES in
CTR mode, especially for larger packet sizes. Area
utilization can further be optimized by using a shared key
expansion module. In IoT and industrial applications, a non-
pipelined sequential approach optimizes hardware space and
improves cycle times at higher clock frequencies. Future
research will focus on optimizing CTR utilization and
integrating an AXI4 interface for physical testing with the
Zynq7000 ARM Cortex-A9 and MicroBlaze processors.
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